1. Field of the Invention.
The present invention relates to integrated circuit technology. More particularly, the present invention relates to slew rate and transient noise control circuits for use in integrated circuits.
2. The Prior Art.
Output buffer circuits are widely used to couple output signals from one integrated circuit to another. Among the important characteristics of an output buffer circuit are the slew rate, or rate of change of output voltage as a function of time, and the transient noise characteristics of the output signal. Both of these characteristics of a digital output signal may materially affect the ability to interface that signal to other devices in a digital system.
Numerous circuits are known in the prior art for controlling the slew rate and altering the transient noise characteristics of the output signal of an output buffer circuit. U.S. Pat. No. 4,789,796 to Foss discloses an output buffer having a sequentially switched output in which single transistors are turned on in sequence to control both pullup and pulldown slew rate of an output buffer. In a first embodiment, cascaded inverters provide the delay and in a second embodiment a falling signal fed to the inputs of three inverters having different voltage switching thresholds provides the delay.
U.S. Pat. No. 4,820,942 to Chan discloses a high drive output buffer with reduced ground bounce. The circuit uses different sized transistors having different turn-off and turn-on speed characteristics which are individually turned on at different times by cascaded inverter delay lines to reduce ground bounce in the output signal.
U.S. Pat. No. 4,885,485 to Leake et al discloses a mask programmable output buffer circuit which includes a plurality of output transistors and a metallization pattern which can be configured to provided cascaded turn on or simultaneous turn on of the plurality of transistors in either the pullup or pulldown configuration. The sources of adjacent pairs of pullup transistors are common and the drains of adjacent pairs of pulidown transistors are common. Custom metallization determines which pairs of pullup transistors have their sources connected to the output node of the buffer and which pairs of pulldown transistors have their drains connected to the output node of the buffer. Continuous distributed-resistance gates are used to provide an RC time delay for the turning on of individual transistors. The gates may be shorted by custom metal lines at intervals along their length corresponding to pairs of both pullup and pulidown transistors to speed up gate signal propagation for pairs of pullup and pulldown transistors.
U.S. Pat. No. 4,918,339 to Shigeo et al. discloses a circuit which sequentially turns on two individual pulidown transistors. The signal which turns on the second transistor is delayed through a delay circuit.
U.S. Pat. No. 4,959,565 to Knecht et al. discloses an output buffer comprising a plurality of pullup or pulidown transistors connected in parallel. A desired amount of resistance is distributed in the gate lines of the transistors, thus providing a distributed RC time delay to sequentially turn on successive individual transistors.
U.S. Pat. No. 4,987,324 to Wong et al. discloses an output buffer circuit with a controlled slew rate. The buffer comprises four inverters, one of which has its P and N channel transistors separately controlled from the outputs of two of the inverters having different switching threshold characteristics.
U.S. Pat. No. 4,992,676 to Gerosa et al. discloses an output buffer comprising a plurality of pullup and pulldown transistors functioning as complementary pairs. Single inverters are used to time cascade the drive signals to the gates of the successive complementary pairs of output transistors.
U.S. Pat. No. 5,036,232 to Jungert et al. discloses a push-pull output buffer stage with successive stages turning on to control slew rate. A distributed RC network comprising discrete resistance elements is used to control successive turn on of complimentary pairs of transistors.
U.S. Pat. No. 5,059,823 to Ahsanullah discloses a supply bounce controlled output buffer circuit. Single pullup and pulldown transistors are controlled by cascaded inverter delay lines from the power supply rails.
U.S. Pat. Nos. 5,111,075 and 5,231,311 to Ferry et al. disclose an output buffer circuit with reduced switching noise. Successive stages comprising complementary transistor pairs are sequentially turned on by an RC time delay network aided by diode bypass networks.
U.S. Pat. No. 5,124,579 to Naghshineh discloses an output buffer with improved ground bounce. Successive stages of complementary transistor pairs are sequentially turned on by an RC time delay network employing transmission gates as the delay elements.
U.S. Pat. No. 5,216,289 to Hahn et al. discloses an output buffer circuit having an output node which may also be used as an input node. The circuit operates by sequentially turning on individual output driver transistors to gradually charge the output node to a high voltage after which the drive to the output driver transistors is turned off.
U.S. Pat. No. 5,329,175 to Peterson discloses an output buffer having multiple stages which are turned on sequentially to avoid transient noise. The circuit operates by sequentially turning on complimentary transistor pairs. Feedforward transistors are used to assure simultaneous turnoff of all pullup and pulldown transistors.
U.S. Pat. No. 5,424,653 to Folmsbee et al. discloses a gradual on output buffer circuit. A plurality of output transistors, gradually increasing in size, are turned off sequentially from the largest to the smallest to reduce VCC bounce.
While the prior art has provided numerous solutions to the problem of providing a controlled slew rate or reduced noise at the output of a digital buffer amplifier, there still remains room for improvement.